Shift in the integration equation
Bill Schweber -- EE Times
(12/24/2007 9:00 AM EST)
The trend of the semiconductor road map has always been to pack more functions on a single die through process shrinks and better processing, bolstered by a larger die itself. This is especially true on the digital side, where economies of scale are easily defined: early CPUs soon expanded to include various types of I/O, buffers, memory and more. But it has also been true on
the analog side, as the "complete" 12-bit D/A converter led to the "really complete" DAC with integrated output buffer and then the "really, truly complete" DAC with internal voltage reference.
At a recent meeting with a leading linear-IC vendor, however, engineers noted that chip-scale packaging (CSP) technologies may be upsetting this IC road map axiom.
(12/24/2007 9:00 AM EST)
The trend of the semiconductor road map has always been to pack more functions on a single die through process shrinks and better processing, bolstered by a larger die itself. This is especially true on the digital side, where economies of scale are easily defined: early CPUs soon expanded to include various types of I/O, buffers, memory and more. But it has also been true on
the analog side, as the "complete" 12-bit D/A converter led to the "really complete" DAC with integrated output buffer and then the "really, truly complete" DAC with internal voltage reference.
At a recent meeting with a leading linear-IC vendor, however, engineers noted that chip-scale packaging (CSP) technologies may be upsetting this IC road map axiom.
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