ISSCC panel sees challenges at 20-nm
Mark LaPedus, EETimes
2/23/2011 9:02 PM EST
During a panel session at the 2011 International Solid-State Circuits Conference (ISSCC) here, IBM, Globalfoundries and TSMC all agreed that they would extend planar bulk CMOS to the 22-/20-nm node. In other words, don’t expect foundries to embrace FinFETs, fully depleted SOI, multi-gate transistors or other newfangled structures at 22-/20-nm.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related News
- Standards group VSIA focuses on adoption challenges
- SIA road map defines performance-SoC challenges
- Object-based video coding challenges MPEG
- Verisity, 0-In and Novas Announce Strategic 'VPA' Collaboration to Address Nanometer SoC Verification Challenges
Latest News
- BrainChip Launches AKD1500 Raspberry Pi 5 Kit: Giving Developers a Direct Path from Prototype to Production
- Cadence Joins the Genesis Mission Consortium to Advance AI-Driven Scientific Discovery and Microelectronics Innovation
- Onsemi picks up Codasip’s low-end RISC-V business for $14.5 million
- Semidynamics and Nokia Explore Collaboration to Strengthen Europe’s Sovereign AI Capabilities
- VeriSilicon Introduces GLTiny™ 3D GPU Programming Model for Ultra-Low-Power, Memory-Efficient Wearable Devices