Cadence links with China designer for IP consulting
Cai Yan, EE Times
(08/09/2006 9:41 AM EDT)
SHANGHAI, China — An IP design center here and Cadence Design Systems Inc. are joining forces to offer IP design-in consultation services for small- and mid-sized chip companies in the Yangtze Delta area.
As part of a deal to buy Cadence tools, Cadence will assign engineers to assist designers at the Shanghai Silicon Intellectual Property Exchange on IP evaluation, validation and SoC design methodologies. The hope is that they can foster an environment where IP is safeguarded and made more affordable for designers to use.
The joint effort will be called the SSIPEX-Cadence IP Research Center. "Our goal is to establish an advanced mixed-signal IP core base and a complete system of IP design, validation and service," a SSIPEX spokesperson said.
(08/09/2006 9:41 AM EDT)
SHANGHAI, China — An IP design center here and Cadence Design Systems Inc. are joining forces to offer IP design-in consultation services for small- and mid-sized chip companies in the Yangtze Delta area.
As part of a deal to buy Cadence tools, Cadence will assign engineers to assist designers at the Shanghai Silicon Intellectual Property Exchange on IP evaluation, validation and SoC design methodologies. The hope is that they can foster an environment where IP is safeguarded and made more affordable for designers to use.
The joint effort will be called the SSIPEX-Cadence IP Research Center. "Our goal is to establish an advanced mixed-signal IP core base and a complete system of IP design, validation and service," a SSIPEX spokesperson said.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related News
- Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology
- Q4 2025 RF Front-End IP: Stable Leaders, China Accelerates, Lansus Enters Top Five, Filters Dominate
- ASIC designer creates design management tool
- ARM links with Synopsys to boost synthesisable core programme
Latest News
- JEDEC Advances DDR5 MRDIMM Ecosystem with New Memory Interface Logic and Expanded MRDIMM Roadmap
- Altera Brings Determinism to Physical AI Systems with Latest Release of FPGA AI Suite
- Mosaic SoC raises $3.8M to bring real-time spatial intelligence to every consumer device
- UMC Reports First Quarter 2026 Results
- Rambus Appoints Sumeet Gagneja as Chief Financial Officer