Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies
SAN JOSE, Calif.— April 25, 2023 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of a node-to-node design migration flow based on the Cadence® Virtuoso® Design Platform compatible with all TSMC advanced nodes, including the latest N3E and N2 process technologies. This new generative design migration flow was jointly developed by Cadence and TSMC to provide a simplified and automated approach to migrate custom and analog IC designs among TSMC’s process technologies. Customers already using the flow have successfully reduced migration time by 2.5X when compared with manual migration.
The Virtuoso Design Platform automatically migrates schematic cells, parameters, pins and wiring from one TSMC process node to another. The Virtuoso ADE Product Suite’s simulation and circuit optimization environment then tunes and optimizes the new schematic to ensure the design achieves all required specifications and measurements.
Cadence and TSMC customers can then automatically recognize and extract groups of devices in an existing layout and apply them to similar groups in the new layout, thanks to the Virtuoso Layout Suite’s generative design technology using templates, TSMC’s analog-mapping and routing technologies in the Virtuoso Design Platform.
“As application requirements grow, many TSMC customers are looking to migrate legacy IC designs to our more advanced nodes, such as N3E and N2, to take full advantage of higher performance and lower power benefits of the latest TSMC advanced technologies,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our ongoing collaboration with Cadence has resulted in enhanced PDKs and methodologies that simplify and accelerate the design migration process, ultimately speeding time to market.”
“Through this latest collaboration with TSMC, our joint customers benefit from our advanced technologies that make custom/analog migration simpler and far less time-consuming,” said Tom Beckley, senior vice president and general manager in the Custom IC, IC Packaging, PCB and System Analysis Group. “Our Virtuoso Design Platform’s proven node-to-node generative design migration technology can shave weeks off the time required to migrate a complex IC design between nodes, which is critical in the highly competitive chip design market.”
The Cadence Virtuoso Design Platform supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about the Virtuoso Design Platform, please visit www.cadence.com/go/virtuosomrgrationN3EN2pr.
About Cadence
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related News
- Cadence Custom/Analog Design Migration Flow Accelerates Adoption of TSMC Advanced Process Technologies
- Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
- Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC’s A16 and N2P Process Technologies
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
Latest News
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
- OpenAI and Broadcom unveil LLM-optimized inference chip