BitSim and Ericsson signs Master Agreement
December 16, 2005 -- Ericsson and BitSim now strengthen their existing cooperation through the Master agreement where BitSim supplies qualified Electronic Design services.
"The agreement enables BitSim to work closer with Ericsson's design teams supporting the projects with leading edge competence" says Anders Sivard, CEO of BitSim AB.
BitSim is a leading consultant and design house in Sweden focusing on electronic design and embedded SW for Board and Chip development. The company has one of Sweden's largest independent electronics development groups.
Four key areas are Chip Design, Digital Signal Processing, High-Speed Design, and Video/Graphics.
"The agreement enables BitSim to work closer with Ericsson's design teams supporting the projects with leading edge competence" says Anders Sivard, CEO of BitSim AB.
BitSim is a leading consultant and design house in Sweden focusing on electronic design and embedded SW for Board and Chip development. The company has one of Sweden's largest independent electronics development groups.
Four key areas are Chip Design, Digital Signal Processing, High-Speed Design, and Video/Graphics.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related News
- Huawei and Ericsson Sign Long-Term Patent Cross-Licensing Agreement
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
- Ericsson boosts the Bluetooth market
- Virage supplies embedded memory technology to Ericsson Microelectronics
Latest News
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
- OpenAI and Broadcom unveil LLM-optimized inference chip
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification