Axilica Offers tool for behavioral synthesis of hardware designs from UML
FalconML is a powerful new tool developed by Axilica to deliver behavioural synthesis of FPGA or ASIC-directed hardware designs from UML. FalconML radically improves designer productivity, allowing electronic chip design companies to:
- Construct complex systems with considerably reduced development times
- Minimise product development costs
- Reach markets ahead of competitors
- Rapidly add key differentiating features.
What is FalconML?
FalconML is a front-end EDA tool that initiates the design process at the UML specification level. It enables true software/hardware partitioning and delivers an output compatible with all EDA back-end flows. The advanced behavioural synthesis engine in FalconML provides routes from UML to both SystemC (for high-performance functional simulation) and to RTL (targeting both FPGAs and ASICs). Silicon IP generated by FalconML can integrate with legacy IP through direct control of design interfaces, allowing such IP to be utilised in new high-performance large-scale VLSI solutions, while taking advantage of the accelerated design process offered by FalconML.
Why use FalconML?
- FalconML automates the flow from specification capture to chip while shortening time to market
- FalconML gives a common starting point for hardware and software design, simplifying co-design and partitioning decisions
- FalconML integrates easily with existing tools and processes
- For software design companies, FaconML gives low cost of entry into hardware design, while end-products operate faster, consume less power and can be miniaturized
- Re-work costs are substantially reduced by performing verification at a higher level of abstraction
Axilica Limited provides products and services to support the rapid development of electronic systems. FalconML is now available for evaluation.
About Axilica Ltd
Axilica has developed a powerful new tool that enables the use of Unified Modeling Language (UML) for the design of electronic hardware. Axilica technology uses model-based techniques to greatly increase designer productivity when implementing today's highly complex electronic systems. Axilica Limited is a spin-out from Loughborough University’s Electrical & Electronic Engineering Department with funding from IPSO Ventures and The Lachesis Fund. Loughborough University Enterprises Limited is also a shareholder.
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- CAST Introduces 400 Gbps UDP/IP Hardware Stack IP Core for High-Performance ASIC Designs
- Axis' Xtreme gets behavioral boost
- Genesys Testware introduces first full chip behavioral test sysnthesis tool
- Sonics Adds New Partners Behavioral Modeling Capability to SOCworks Website
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’