Barcelona Accelerates IP Creation with New Op Amp Engine
Picasso™ Class Building Block Engines added to Barcelona’s IP Portfolio
Newark, Calif., January 14, 2003 - Barcelona Design Inc., the leading provider of synthesizable full-custom analog IP, today announced the release of a new IP product, the Picasso™ Class Building Block Engines. The first engine to be released in this class, the Picasso BOAS11-18 Op Amp Engine has been shipped to a leading consumer electronics provider in Japan, and is based on extensive silicon results of both standalone op amps and more complex components.
The Picasso BOAS11-18 Op Amp Engine works with the Prado™ Synthesis Platform to synthesize fully customized, tapeout-ready operational amplifiers, a key building block for all types of analog circuits including voltage regulators, phase-locked loops (PLLs) and data converters. With the ability to choose from ten different op amp topologies or architectures, chip designers can produce optimal designs in a matter of minutes rather than weeks.
The majority of analog design flows lack automation, leaving highly skilled designers to iterate manually towards a solution in several phases of the move from idea to implementation, thus resulting in delayed production cycles. Barcelona Design's synthesizable, full-custom analog circuit IP solutions enable digital and analog engineers to create optimized mixed-signal components and achieve dramatically faster design times.
"The Picasso Op Amp Engine is an important addition to our product portfolio. Barcelona is thrilled that yet another major electronics firm has chosen to adopt our IP technology," said Peter Santos, vice president of Marketing and Business Development at Barcelona. "We are at the forefront of an important shift in our industry. Barcelona’s customized analog IP solution eliminates the need for painstaking, time-intensive iterations and allows designers a high-level of productivity, resulting in dramatically faster time to market."
The Picasso Op Amp Engine offers support for 0.18 µm CMOS processes. It provides a choice of ten different single-ended topologies targeted for low noise, high gain, and loop bandwidths approaching 1 GHz. Optimization objectives for this engine include power, unity gain bandwidth and area. The engine is well suited to use in applications such as DVDs, wireless phones & LANs, and ethernet-based systems.
The Picasso BOAS11 –18 Engine is compatible with all versions of Barcelona’s Prado Synthesis Platform, and is currently available. For more information, contact Barcelona at 510-897-1800 or send an email to info@barcelonadesign.com.
About Barcelona Design, Inc.
Barcelona Design is the leading supplier of synthesizable full-custom analog circuits, offering unique semiconductor intellectual property complemented by powerful design technology. Barcelona was founded in 1999 by CTO Dr. Mar Hershenson and Stanford University professor Dr. Stephen Boyd as a result of their research on the application of convex optimization mathematics to analog circuit design. The firm’s analog circuit solution enables electronics companies to implement complex intellectual property (IP) instances radically faster than ever before. The company has proven its technology with working silicon, and has demonstrated market acceptance of its innovative approach by winning key customers. Barcelona has secured financing from leading venture capitalists including, Crosslink Capital, Sequoia Capital and Foundation Capital. The firm is headquartered in Newark, CA. For more information please visit www.barcelonadesign.com.
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Q4 2025 RF Front-End IP: Stable Leaders, China Accelerates, Lansus Enters Top Five, Filters Dominate
- BSC presents Sargantana, the new generation of the first open-source chips designed in Spain
- Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-V
- Lightmatter Collaborates with Synopsys to Integrate Advanced Interface IP with Its Passage Co-Packaged Optics Platform
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’