Atomic Rules Becomes a Community Member of the Open Core Protocol International Partnership
AUBURN, NH - January 5, 2009 - Atomic Rules LLC announced today that it has joined the Open Core Protocol International Partnership (OCP-IP) as a community member, to actively participate in the implementation and evolution of the standard.
"There are many tough challenges in building complex digital systems, naming the signals that interconnect IP cores should not be one of them", said Shep Siegel, CTO of Atomic Rules.
By joining OCP-IP, Atomic Rules hopes to elevate conventional RTLs, which can be plagued by weakly-defined implicit assumptions; to the less error-prone, correct-by-construction, standard calling conventions of Bluespec SystemVerilog (BSV).
Atomic Rules LLC is a New Hampshire based consultancy that provides strategic capabilities for reconfigurable computing.
www.atomicrules.com
"There are many tough challenges in building complex digital systems, naming the signals that interconnect IP cores should not be one of them", said Shep Siegel, CTO of Atomic Rules.
By joining OCP-IP, Atomic Rules hopes to elevate conventional RTLs, which can be plagued by weakly-defined implicit assumptions; to the less error-prone, correct-by-construction, standard calling conventions of Bluespec SystemVerilog (BSV).
Atomic Rules LLC is a New Hampshire based consultancy that provides strategic capabilities for reconfigurable computing.
www.atomicrules.com
Related Semiconductor IP
- 1.6T Ultra Ethernet Controller
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
Related News
- Atomic Rules Joins the 25 Gigabit Ethernet Consortium
- BittWare and Atomic Rules announce an FPGA-based UDP Offload Engine IP Core for 10/25/50/100 GbE
- Atomic Rules announces DPDK-aware FPGA/GPP data mover
- Atomic Rules launches TimeServo System Timer IP Core for FPGA
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA