ASICLAND Joins 2025 TSMC OIP Forum, Expanding Its Role in the Global Semiconductor Ecosystem

• Second consecutive participation, sharing insights on 2nm, AI, and 3DIC technologies
• Strengthening collaboration with TSMC and OIP partners to accelerate advanced design and packaging projects
• Showcasing AxHub™, High-Performance SoC, and Chiplet platforms for customized ASIC development

November 19, 2025 -- ASICLAND announced its participation in the 2025 TSMC Global Open Innovation Platform (OIP) Ecosystem Forum in Taiwan, reinforcing its role as Korea’s leading ASIC design partner within the global semiconductor value chain.

The TSMC OIP Ecosystem Forum is a global event hosted by TSMC, the world’s largest semiconductor foundry, held annually across North America, Taiwan, Japan, China, and Europe. The 2025 forum brings together more than 5,000 semiconductor experts and over 750 companies—including TSMC partners, EDA vendors, IP providers, and OSAT firms—to discuss the latest technologies, methodologies, and design enablement strategies.

This year’s forum highlights next-generation technologies such as TSMC A16*, advanced 2nm and 3nm processes, and TSMC’s 3DFabric® 2D/3DIC integration technologies (InFO, CoWoS®, SoIC®, SoW™). Key sessions also cover AI-powered EDA automation, low-power design, application-specific IP solutions, and cloud-based design workflows aimed at reducing time-to-market for semiconductor products.

_{* TSMC A16: A next-generation ~1.6nm-class process technology that enhances speed, power efficiency, and chip density through an advanced backside power delivery architecture.}

As Korea’s only TSMC VCA (Value Chain Alliance) partner, ASICLAND plans to leverage the forum to strengthen technical collaboration with TSMC and global OIP ecosystem partners. Backed by the capabilities of its Taiwan R&D Center, ASICLAND aims to expand joint development projects covering 2/3/5nm nodes, advanced packaging, and chiplet-based architectures.

At the event, ASICLAND showcases its three flagship platforms:

• AxHub™ Platform — enabling rapid ASIC development through pre-verified interface dies
• High-Performance SoC Platform — optimized for AI and HPC workloads using 5nm Arm-based architecture
• Chiplet Platform — leveraging TSMC CoWoS® to connect HBM and logic dies for high-bandwidth, low-power systems

These platforms are designed to be interoperable, allowing customers—from emerging fabless companies to global enterprises—to scale their performance, integration level, and development timeline with flexibility.

▲ ASICLAND, 2025 TSMC OIP Ecosystem Forum

“TSMC OIP is the most important venue for understanding technology directions, ecosystem strategies, and collaboration opportunities in the global semiconductor industry,” said Jong-min Lee, CEO of ASICLAND. “We will continue to advance our capabilities in leading-edge process technologies and global co-development to strengthen our position as a trusted ASIC design partner worldwide.”

ASICLAND’s Taiwan R&D Center recently marked its first anniversary, achieving major milestones including the establishment of a 2nm/3nm design environment and 3DIC packaging development through close cooperation with TSMC.