Apache Design's Totem Software Adopted by Fujitsu Semiconductor for Power Noise and Reliability Analysis
Solution from ANSYS Subsidiary Addresses Accuracy, Performance and Capacity for Advanced Process Custom IC Designs
PITTSBURGH – December 7, 2011 – ANSYS (NASDAQ: ANSS) announced that Totem™ software — from its subsidiary Apache Design, Inc. — has been deployed by Fujitsu Semiconductor Limited to analyze and optimize all their custom integrated circuit (IC) designs. This includes analog, memory, high-speed I/O, PMIC (power management IC) and RF ICs that are used in wide variety of consumer, mobile and communications electronic products. As custom IC designs increase in complexity, engineers face the challenges of meeting stringent performance and reliability targets, especially at 28-nanometer (nm) and below manufacturing process nodes. Totem — a complete power noise and reliability platform for analog/mixed-signal chip designs — was selected by Fujitsu Semiconductor for its ability to handle large designs and analyze global noise coupling, which can impact chip performance and reliability. It was also chosen for its integration with existing analog design tool environments, a feature that offers improved productivity.
"Apache’s Totem enables us to accurately model and simulate power/ground, substrate and package/PCB noise coupling at the full-chip level for advanced process technologies," said Masaru Ito, director of the technology development division, IP and technology development and manufacturing unit of Fujitsu Semiconductor Limited. "By using Totem, we can explore the impact of noise coupling on the circuit’s performance and determine if critical layout changes are needed early in the design process, allowing us to increase productivity and lower the risk of re-spin."
"The successful adoption of our Totem platform demonstrates how designers can depend on Apache to deliver products that meet the needs of leading custom designs," said Dian Yang, general manager and senior vice president at Apache. "Totem enables designers to optimize for better performance, lower product cost, meet specifications, and help mitigate design risks."
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related News
- Apache and Xilinx Unveil Unique Signal Integrity Analysis Tool for Virtex-II Pro Based Multi-Gigabit Serial I/O Designs
- Wi-LAN Completes Sale of Technology Development Division to Fujitsu Microelectronics America; Final Agreement Reflects Wi-LAN's Transition into a Licensing Company
- Fujitsu, NEC Electronics, Renesas, and Toshiba to Aim for Standardization of Semiconductor Process Technology for Next-Generation LSI
- Fujitsu Introduces Its Mobile WiMAX System-on-Chip Solution and Roadmap
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA