Altera bases 45-nm success on TSMC relationship
Nicolas Mokhoff, EE Times
(10/09/2007 1:51 PM EDT)
NEW YORK — Altera and TSMC are at it again. Altera's next venture into a family of FPGAs that will be produced in the 45-nm process node is riding on the success of its earlier 65-nm successful relationship with foundry TSMC.
Two years ago, Taiwan Semiconductor Manufacturing Co. Ltd. unveiled its 65-nm manufacturing process and FPGA maker Altera and others were taping out 65-nm designs. The first 65-nm process was optimized for low power, followed by a high-speed version. The 65-nm process already included the use of strained silicon and nickel silicide, low-k dielectrics and copper interconnects.
(10/09/2007 1:51 PM EDT)
NEW YORK — Altera and TSMC are at it again. Altera's next venture into a family of FPGAs that will be produced in the 45-nm process node is riding on the success of its earlier 65-nm successful relationship with foundry TSMC.
Two years ago, Taiwan Semiconductor Manufacturing Co. Ltd. unveiled its 65-nm manufacturing process and FPGA maker Altera and others were taping out 65-nm designs. The first 65-nm process was optimized for low power, followed by a high-speed version. The 65-nm process already included the use of strained silicon and nickel silicide, low-k dielectrics and copper interconnects.
To read the full article, click here
Related Semiconductor IP
- Ultra-low jitter, low-power ring-oscillator-based PLL-3GHz-4GHz
- Image Warping IP
- Image Warping IP
- ML-KEM-X Post-Quantum Cryptography Core
- AXI5 to/from AXI4 Bridge
Related News
- Altera Speeds IEC 61508-compliant Designs with Certified 28 nm FPGAs, SoCs, and Toolflows
- Philips Semiconductors and ARM Expand Relationship With Long-Term Licensing Agreement
- ATMOS and MOSAID build on DRAM compiler relationship
- Mentor Graphics and Artisan Components Enter into Strategic Relationship to Deliver Total System-on-Chip IP Solution <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
Latest News
- ASYGN Revolutionizes Ultra-Low-Power Embedded AI with Its ColibryNPU Microcontroller
- Tampere University Joins OpenTitan Coalition to Advance RISC-V SoC Security and Open-Source Silicon Research
- Kandou AI to Open India Chip Design Headquarters in Hyderabad
- CAST Expands Functional Safety IP Line with ASIL B Ready SENT/SAE J2716 Receiver Core
- SkyeChip Advances Custom Interface IP Engagement with Cerebras for Wafer-Scale AI Platforms