Altera announced two IP cores for DSP
IP cores for DSP
By David Larner - Embedded Systems,
March 21, 2001 (12:18 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010321S0020
Altera announced two intellectual property (IP) cores for the digital signal processing (DSP) marketplace for implementation on the company's programmable logic devices (PLDs). These cores are designed for the communications applications. Each signal processing IP core has been rigorously tested and meets the requirements of IEEE and other communications standards setting bodies. One is an infinite impulse response (IIR) structure that has been developed to meet the needs of automatic gain control circuits (AGC), Goertzel algorithm implementation, digital direct synthesis, or cascaded integrated comb (CIC) filters. The IIR order 2 filter, for industrial control applications, can be implemented in Altera's APEX EP20K30E devices
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