Alps Alpine Adopts Silvaco’s Jivaro Pro to Accelerate SPICE Post-Layout Simulation 2025-05-13 14:52:00 EDA & Design Tools
Siemens leverages AI to close industry’s IC verification productivity gap in new Questa One smart verification solution 2025-05-13 14:06:00 EDA & Design Tools
Union Minister Shri Ashwini Vaishnaw Unveils India’s First 3nm Chip Design Centres in Noida and Bengaluru 2025-05-13 08:11:00 Strategic Partnerships
Axiomise Featured Gold Sponsor at RISC-V Summit Europe Next Week in Paris 2025-05-12 11:30:00 Events & Conferences
See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit 2025-05-12 11:22:00 Events & Conferences
RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027 2025-05-12 10:04:00 Analysis & Insight
Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025 2025-05-12 09:04:00 Events & Conferences
PQSecure Partners with Menta to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric 2025-05-11 08:26:00 IP Cores & Design
Skymizer Launches HyperThought: Build Your Own AI Chip with Skymizer’s LPU IP 2025-05-09 14:44:00 IP Cores & Design
SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors 2025-05-09 10:45:00 SoC Architecture & Assembly
Panmnesia Kicks off $30M Project to Redefine AI Infrastructure with Chiplets, Manycore Architectures, In-Memory Processing, and CXL 2025-05-08 14:07:00 Strategic Partnerships
SEGGER and Quintauris are working together to develop products and technology for the open-source RISC-V ecosystem 2025-05-08 14:02:00 SoC Architecture & Assembly
Arm Reports Quarterly Revenue of Over $1 Billion for First Time in Company’s History 2025-05-08 07:05:00 Financials
VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard 2025-05-08 06:37:00 Standards & Interconnects