BrainChip and HaiLa Partner to Demonstrate Ultra-Low Power Edge AI Connectivity for IoT Sensor Applications
2025-06-24 13:22:00
SoC Architecture & Assembly
Semiconductor IP News Archive - Page 50 of 1948
Creonic's DVB-S2X/S2 IP Cores Now Support the New DVB-NIP Standard
2025-06-24 12:09:00
IP Cores & Design
Ceva Launches MotionEngine™ Hex: Bringing Precise, Touch-Free, Spatial Control to Smart TV, Gaming, and IoT Interfaces
2025-06-24 11:45:00
SoC Architecture & Assembly
SEALSQ, ColibriTD, and Xdigit Announce Plan to Develop a Breakthrough Quantum Computing Based Solution Set to Revolutionize Semiconductor Wafer Yields for Sub-7nm Nodes
2025-06-24 11:39:00
SoC Architecture & Assembly
Faraday Delivers Latest SerDes IP to Complete Interface Lineup on UMC’s 22nm Platform
2025-06-24 08:36:00
IP Cores & Design
Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025
2025-06-23 17:01:00
EDA & Design Tools
Yocto Project Welcomes RISC-V International as New Platinum Member, Expands Global Ecosystem and Leads with Cyber Resilience Act Preparedness
2025-06-23 15:45:00
SoC Architecture & Assembly
Continental to Create an Advanced Electronics & Semiconductor Solutions Organization
2025-06-23 15:26:00
Strategic Partnerships
Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
2025-06-23 13:02:00
EDA & Design Tools
Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI
2025-06-23 12:55:00
EDA & Design Tools
Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization
2025-06-23 11:32:00
EDA & Design Tools
Rapidus announces collaboration with Siemens for 2nm semiconductor design
2025-06-23 10:19:00
EDA & Design Tools
Caspia Technologies Collaboration to Enhance Security Verification in Siemens' Questa One With Caspia's Generative AI Security Platform
2025-06-23 10:07:00
EDA & Design Tools
True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL
2025-06-23 07:35:00
IP Cores & Design
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
2025-06-20 08:26:00
Events & Conferences
Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
2025-06-20 07:54:00
SoC Architecture & Assembly
Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
2025-06-19 17:36:00
EDA & Design Tools
CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
2025-06-19 10:09:00
IP Cores & Design
ZeroRISC Gets $10 Million Funding, Says Open-Source Silicon Security ‘Inevitable’
2025-06-19 09:11:00
Analysis & Insight
BT Group Joins the CHERI Alliance to Advance Cybersecurity Innovation
2025-06-18 20:54:00
Standards & Interconnects