EU's INTERESTED project to target the rapid design, prototyping and code generation of complex embedded systems and software 2009-02-25 07:36:00 Misc
NextIO Adopts Denali's Verification IP for New PCI Express Expansion and I/O Virtualization Module for Blade Systems 2009-02-24 21:36:00 Commercial Deals
Certess Announces The First C-Level Functional Qualification Tool 2009-02-24 17:50:00 EDA & Design Tools
Synopsys, Powerchip and Nikon Collaborate on 42-nm Flash Memory Optimization 2009-02-24 16:34:00 EDA & Design Tools
Court Grants Rambus Supplemental Damages in Hynix Case and Orders Negotiation of Compulsory License 2009-02-24 16:25:00 Legal & IP Strategy
United States Supreme Court Denies FTC Request to Review Rambus Matter 2009-02-24 16:22:00 Legal & IP Strategy
Lattice Launches Industry's Lowest Power, Highest Value FPGA Devices 2009-02-23 16:17:00 SoC Architecture & Assembly
Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support 2009-02-23 14:18:00 Verification IP
Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and Higher Value for SoC Developers 2009-02-23 14:17:00 Verification IP
Intelop announces major enhancements to their TCP-Offload Engine SoC IP that has integrated GEMAC, ARP module and AMBA 2.0 bus and PCIe interface running at 2-Gbps also is capable of managing thousands of simultaneous TCP sessions in realtime 2009-02-23 12:58:00 IP Cores & Design
ARM Launches Its Smallest, Lowest Power, Most Energy Efficient Processor 2009-02-23 11:44:00 IP Cores & Design
Jasper Design Automation Introduces Design Activation Services To Promote IP and Design Reuse, Driving Higher Customer ROI 2009-02-23 08:22:00 EDA & Design Tools
Industry's First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available 2009-02-23 07:15:00 Misc
Aspex Semiconductor reaches profitability - wins significant contracts 2009-02-20 16:32:00 Strategic Partnerships