Verification of Light Weight Forward Error Correction (FEC) and Strong Cyclic Redundancy Checks (CRC) feature in PCIe 6.0
In 2021, PCI-SIG® released the latest version of the PCI Express® specification PCIe® 6.0. PCIe 6.0 has a raw data rate of 64 GT/s and double the bandwidth of PCIe 5.0 (32GT/s) to meet industry demand for a high-speed, low latency interconnect. It is a scalable interconnect solution for data-intensive markets like data centers, AI/ML, high-performance computing (HPC), and automotive.
In our recent blog, PCI Express Surges Forward: High Bandwidth Interconnect with PCIe 6.0 we talked about the changes that are introduced in PCIe 6.0. In this blog we will discuss the Forward Error Correction (FEC) mechanism in PCIe 6.0, why it is required, and what verification solution Synopsys offers to cover this feature.
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 Retimer Controller with CXL Support
- PHY for PCIe 6.0 and CXL
- PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
Related Blogs
- Demystifying Forward Error Correction (FEC) in PCIe 6.0
- Streamline PCIe 6.0 Switch Design with Effective Verification Strategies
- Unraveling the Newly Introduced Segmentation in PCIe 6.0
- PCIe 6.0 Address Translation Services: Verification Challenges and Strategies
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins