TSMC Restrictive Design Rules and 32/28nm Yield
To follow up one of my most viewed blogs: TSMC 40nm Yield Explained, let’s talk about Restrictive Design Rules (RDRs) and 32/28nm yield. RDRs have been seriously discussed since 65nm, by restricting the freedom layout designers enjoy today a foundry can better guarantee the manufacturability of a semiconductor design. RDRs even have a Wikipedia page.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
- Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- How Cadence and TSMC Are Accelerating AI Silicon Design at Advanced Nodes
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing