TSMC Restrictive Design Rules and 32/28nm Yield
To follow up one of my most viewed blogs: TSMC 40nm Yield Explained, let’s talk about Restrictive Design Rules (RDRs) and 32/28nm yield. RDRs have been seriously discussed since 65nm, by restricting the freedom layout designers enjoy today a foundry can better guarantee the manufacturability of a semiconductor design. RDRs even have a Wikipedia page.
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