The Future of Fabless Design?
September 20, 2012
Lately, there has been a rise in predictions that the fabless business model is “dying”, or “collapsing”, or simply that it “no longer works”. The main argument centers on the disconcerting fact that a disaggregated supply chain makes optimization of the semiconductor product increasingly difficult to achieve, especially when coupled with the inherent complexity of advanced process nodes and leading-edge designs. In particular, the data interfaces between design teams, foundries, and EDA vendors are becoming increasingly complex. The result is a dramatic increase in cost, and more importantly, risk.
To read the full article, click here
Related Semiconductor IP
- Adaptive Voltage Scaling (AVS) Bus Target IP
- Adaptive Voltage Scaling (AVS) Bus Host Controller
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Related Blogs
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
- Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design
- Shaping the Future of Semiconductor Design Through Collaboration: Synopsys Wins Multiple TSMC OIP Partner of the Year Awards
- How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects