Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area.
The PCIe standard has been around for nearly 20 years. A diverse range of applications, bandwidth needs, and form factors drive the need for rate scaling of the protocol.
To read the full article, click here
Related Semiconductor IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 Controller with AXI
- PCIe 5.0 Controller
- PCIe 5.0 Multi-port Switch
- PCIe 5.0 PHY NCS in TSMC (N7, N6, N5)
Related Blogs
- The Next-Generation UCIe IP Subsystem for Advanced Package Designs
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
Latest Blogs
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC