Simplifying the Usage of UVM Register Model
When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers. I also felt that the terms used do not reflect the intent precisely. After spending some time, I came up with a table which helped me to understand the behavior of register model APIs, and how best they can be called.
Before I introduce the table, let us take a look at the process of creating the register model:
- Creating the register format specification
- Converting the specification into UVM register model
- Using the register model
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