Simplifying the Usage of UVM Register Model
When I began using UVM RAL, I could not understand what the UVM base class library had to say about updating the values of desired value and mirror value registers. I also felt that the terms used do not reflect the intent precisely. After spending some time, I came up with a table which helped me to understand the behavior of register model APIs, and how best they can be called.
Before I introduce the table, let us take a look at the process of creating the register model:
- Creating the register format specification
- Converting the specification into UVM register model
- Using the register model
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Building the Future of AI on Intelligent Accelerators
- Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design
- Unleashing the Power of Wi-Fi 7. Multi-Link Operation Configurations Demystified
- Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update
Latest Blogs
- Pioneering Secure-by-Design in the Age of the European CRA
- Overcoming power management IP challenges
- Running OpenCode with llama.cpp and Qwen 3.5 on E-Series
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus