Taking a closer look at the Rambus GDDR6 PHY IP Core

By Rambus Inc.

February 1, 2018

Once targeted exclusively at GPUs, GDDR use cases are rapidly expanding beyond traditional GPU and graphic applications. This is primarily due to the demand for increased bandwidth across a diverse set of market verticals – including the data center and automotive sector. GGDR6 can help meet that demand.

Bandwidth and SI challenges

More specifically, DDR4 currently tops out at 3.2 Gb/s, while a maximum interface speed of 8 Gb/s is achievable with GDDR5. In contrast, GDDR6 devices will double interface speed to 16 Gb/s. Put simply, GDDR6 is expected to provide 5x the speed per pin of leading-edge DDR4, with the Rambus GDDR6 PHY supporting speeds up to 16Gbps per pin, across two 16bit channels to provide a maximum bandwidth of 512 Gbps (or 64GB/s).

With GDDR6 providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that devices and systems aren’t affected by signal integrity issues. This is precisely why the Rambus GDDR6 PHY engineering team makes extensive use of modeling and simulation tools, as well as providing highly programmable circuits, debug interfaces and utilities. Moreover, our engineering team comprises a range of in-house experts that participate in all stages of the GDDR6 PHY design which will be available on leading FinFET process nodes. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.

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