Performance in Hardware Emulators: System Architecture
In my previous post, Performance in Hardware Emulators, I discussed the dependency of performance on the type of deployment. In this column, I will examine the relationship between emulation system architectures and their performance.
Emulation performance vs. Emulator architecture
Not all emulators are created equal. Previously, I pointed out that the design capacity and the compilation process are dependent on the architecture of the emulation system. This is also the case for emulation performance.
Let's remind ourselves that each of the current three hardware emulation suppliers is promoting its own architecture:
- Cadence: Processor-based architecture
- Mentor: Custom emulator-on-chip architecture
- Synopsys: Commercial FPGA-based architecture
While the first two solutions are based on custom chips, the third is built on arrays of commercial FPGAs.
To read the full article, click here
Related Semiconductor IP
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
Related Blogs
- Performance in Hardware Emulators
- Relationship between architecture and validation in system design
- Why Hardware Security Is Just as Critical as Software Security in Modern Systems
- Understanding Design Capacity in Hardware Emulators
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects