Performance in Hardware Emulators: System Architecture

By EETimes

September 10, 2015

In my previous post, Performance in Hardware Emulators, I discussed the dependency of performance on the type of deployment. In this column, I will examine the relationship between emulation system architectures and their performance.

Emulation performance vs. Emulator architecture
Not all emulators are created equal. Previously, I pointed out that the design capacity and the compilation process are dependent on the architecture of the emulation system. This is also the case for emulation performance.

Let's remind ourselves that each of the current three hardware emulation suppliers is promoting its own architecture:

• Cadence: Processor-based architecture
• Mentor: Custom emulator-on-chip architecture
• Synopsys: Commercial FPGA-based architecture

While the first two solutions are based on custom chips, the third is built on arrays of commercial FPGAs.

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