PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted?
The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitment to the accelerated development of PCIe 5.0.
PCIe 5.0 rev 0.7 is published and already out for membership review as of May. The big-ticket item is, of course, support for 32GT/s.
To read the full article, click here
Related Semiconductor IP
- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
- PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
- PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
- PCIe 5.0 (Gen5) Premium Controller with AMBA bridge II
Related Blogs
- PCI Express takes on Apple/Intel Thunderbolt and 16 Gtransfers/sec at PCI SIG while PCIe Gen 3 starts to power up
- PCI Express 5 vs. 4: What's New? [Everything You Need to Know]
- Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
- 1, 2, 3, 4, 5... It's Official, PCIe 5.0 is Announced
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions