Myths, hype and the building blocks of SoCs

By EETimes

November 9, 2012

I was on a product introduction call the other with some of the folks at Synopsys and they put up a slide that showed the amounts of reuse in a typical chip. This was not central to the main discussion, but it struck me as being out of whack with conventional messaging I have been hearing about for the past decade or more about IP, reuse and design costs. Here is the chart from that presentation.

The source cited was Semico from June 2010. I looked at the bar for 2011 (not much of a projection) and was surprised by two things – reuse only accounted for 20 percent of the chip and that figure was decreasing, although at a slower rate than the decrease in new logic. I have heard so many people talk about a chip being 90 percent reuse and even if we count the memory as reuse, that only gives 80 percent and even by 2017 it is not expected to be 90 percent. So what is the reality?

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