Introduction of Precoding in PCIe 6.0

By Cadence

June 29, 2023

What Is Precoding in PCIe?

With higher speed introduced from PCIe 5.0, high 32.0 GT/s insertion loss target (-36dB) leads to a higher DFE tap ratio which, in turn, may trigger burst errors due to error propagation following a single bit error. Because of a high DFE tap ratio, if a bit flips and the data is a 01010 pattern, then the bit that flipped influences the DFE the wrong way, so it flips the next bit, which then influences the next bit, and so on... the problem corrects if bits did not alternate since the DFE would settle properly. Burst errors can eventually break the CRC detection capability. They can also lead to SKP Ordered Set corruption

Precoding concept is introduced in PCIe 5.0 Spec and defined new precoding logic for 2-bit aligned UI level (PAM4 used in PCIe 6.0). A Receiver may request precoding from its transmitter for operating at data rates of 32.0 GT/s and higher. Precoding, when enabled at a Data Rate, applies to both Flit Mode and Non-Flit Mode at that data rate.

What’s New for Precoding at 64.0 GT/s and Higher Data Rates ?

To read the full article, click here