Insights Into the Evolutions and Optimizations of PCIe 6.0
The PCIe protocol (Peripheral Component Interconnect Express) had its first generation in 2003, being a huge breakthrough in the industry by allowing up to 2.5 GT/s per lane in a serial computer expansion bus. The protocol has since evolved many times, always doubling its transfer rate compared to the previous generation and bringing new features and optimizations whenever needed.
The latest release was announced in 2022, in which PCIe 6.0 was introduced with up to 64.0 GT/s speed per lane. As was announced at the PCI-SIG Developers Conference in San Jose, 2023, PCIe 6.0 not only again doubled the speed but also prepared the grounds for many generations to come. The changes were made considering many necessary optimizations to the existing rules, considering the industry usage and experience of 20 years. New concepts and technologies were introduced, such as 1b/1b encoding, PAM4 modulation, and Flit Mode operation.
To read the full article, click here
Related Semiconductor IP
- PCIe 6.0 Retimer Controller with CXL Support
- PHY for PCIe 6.0 and CXL
- PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
Related Blogs
- The Evolution of CXL.CacheMem IDE: Insights into CXL3.0 Security Feature
- Trust at the Core: A Deep Dive into Hardware Root of Trust (HRoT)
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC
- CNNs and Transformers: Decoding the Titans of AI
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car