Improve Your Verification Methodology: Hunt Bugs Flying in Squadrons
March 14, 2022
Creating a quality RISC-V processor requires a verification methodology that enforces the highest standards. In this article, Philippe Luc, Director of Verification at Codasip, explains the methodology that is adopted at Codasip to bring processor verification to the next level.
After analyzing bugs on several generations of CPUs, I came to the conclusion that “bugs fly in squadrons”. In other words, when a bug is found in a given area of the design, the probability that there are other bugs with similar conditions, in the same area of the design, is quite high.
To read the full article, click here
Related Semiconductor IP
- 64-Bit 8-stage superscalar RISC-V processor
- Multi-core capable RISC-V processor with vector extensions
- 32 Bit - Embedded RISC-V Processor Core
- ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
Related Blogs
- Programmable Hardware Delivers 10,000X Improvement in Verification Speed over Software for Forward Error Correction
- Measuring the complexity of processor bugs to improve testbench quality
- Accelerating Your Overall HW/SW Verification and Validation Productivity Using Dynamic Duo
- Using Synopsys Smart Monitors to Improve System Performance of Your Arm SoCs
Latest Blogs
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car