How to Meet Self-Driving Automotive Design Goals Part 1
Achronix anticipates that the favored self-driving architecture of the future will be increasingly decentralized. However, both the centralized and decentralized architectural design approaches will require hardware acceleration in the form of far more lookaside coprocessing than is currently realized. Whether centralized or decentralized, the anticipated computing architectures for automated and autonomous driving systems will clearly be heterogeneous and require a mix of processing resources used for tasks ranging in complexity from local-area-network control, translation, and bridging to parallel object recognition based on deep-learning algorithms running on neural networks. As a result, the current level of more than 100 CPUs found in luxury piloted vehicles could easily swell to several hundred CPUs and other processing elements for more advanced, autonomous vehicles.
To read the full article, click here
Related Semiconductor IP
- JESD204C IP
- Embedded FPGA
- Chacha20-Poly1305 IP for FPGA and ASIC
- Configurable Ascon IP for FPGA and ASIC
Related Blogs
- How to Meet Self-Driving Automotive Design Goals Part 2
- How to design secure SoCs Part IV: Runtime Integrity Protection
- The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
- Cycuity Partners with SiFive and BAE Systems to Strengthen Microelectronics Design Supply Chain Security
Latest Blogs
- From Bug Hunting to Engineering Methodology: Lessons from AI-Driven Development
- Manufacturing Intelligence: Turning EDA Data into Trusted Action
- Execute-in-Place: Getting More from Embedded NVM
- Rethinking RTL flows with AI-driven hybrid formal verification
- Arm and NVIDIA: Building the trusted compute foundation for the agentic AI era