HBM controller IP holds the key to bandwidth
July 1, 2016
We were waiting to see what a different roster including SK Hynix and Synopsys would have to say on HBM in the latest Open Silicon webinar. This event focused on HBM bandwidth issues; a packaging session on 2.5D interposers was promised for a future webinar.
For their part, the SK Hynix story on HBM is the same. GDDR5X parts (from Micron) are just hitting the ground, fitting into the external memory model the industry is used to. Breaking that model with HBM2 and multi-die packaging can blow GDDR5X away in theoretical bandwidth with some attention to details.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Rambus LPDDR5T/5X/5 Controller IP Turbocharges AI Inference Performance to 9.6 Gbps
- Breaking the Bandwidth Barrier: Enabling Celestial AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform
- Rambus HBM3 Controller IP Gives AI Training a New Boost
Latest Blogs
- A Repeatable Framework for Hardware Security Assurance
- Inside the SiFive Performance™ P570 Gen 3: High Performance Efficiency for Next-Generation Consumer and Commercial Applications
- What the steam engine can teach us about modern chip design
- Automotive silicon in the era of AI, functional safety, and cybersecurity
- JPEG XS Officially Joins GenICam, The Machine Vision Standard Managed By EMVA