HBM controller IP holds the key to bandwidth
July 1, 2016
We were waiting to see what a different roster including SK Hynix and Synopsys would have to say on HBM in the latest Open Silicon webinar. This event focused on HBM bandwidth issues; a packaging session on 2.5D interposers was promised for a future webinar.
For their part, the SK Hynix story on HBM is the same. GDDR5X parts (from Micron) are just hitting the ground, fitting into the external memory model the industry is used to. Breaking that model with HBM2 and multi-die packaging can blow GDDR5X away in theoretical bandwidth with some attention to details.
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Related Semiconductor IP
- HBM Memory Model
- HBM 4 Verification IP
- HBM 3 Verification IP
- HBM Memory Controller
- Verification IP for HBM
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