Deciphering the New TileLink Standard

By Synopsys, Inc.

January 27, 2020

Increasing complexities of processor architectures with limited overall performance scale-up have created a demand for a domain specific architecture to ensure extensive performance scaling. – this is when RISC-V began to gain momentum. RISC-V is gathering widespread attention throughout sectors like datacenter accelerators, mobile & wireless, IoT, etc. for its extensibility. Many industry leaders are beginning to adopt RISC-V for its open source availability that reduces time-to-market and cost effectiveness while at the same time scaling up the overall performance and leaving room for innovation and automation.

TileLink is an open standard chip-scale interconnect designed to be used with RISC-V processors. It also supports other ISAs.

TileLink is an easy to implement cache-coherent bus protocol that can be utilized in a System-on-Chip (SoC) to connect accelerators, general purpose multiprocessors, co-processors, DMA engines and simple or complex designs.

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