Cortex-M7: 6-stage, cached, 400 MHz MCU

By SemiWiki

October 1, 2014

“Who needs a 32-bit MCU?” It was a question asked a million times in the press when ARM introduced the Cortex-M family back in 2004. In fairness, that question predates the Internet of Things, with wireless sensor networks, open source code, encryption, and more needs for connected devices.

In the beginning, it was about matching the MCU incumbents – 8051, AVR, HC11, MSP430, PIC, and others. The discussion always seemed to be centered on package pin counts, and sleep currents, and less than $1 in volume pricing, and code efficiency. Nobody would ever need 32-bit address space, or faster memory, or floating point, or really fast cores, especially if they drove power consumption the wrong direction.

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