Complete Memory Interface Solution for HBM2E Launched
Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack.
HBM2E Memory System with Single DRAM Stack
In addition to the speed jump from 2.0 to 3.2 Gbps for HBM2E vs. HBM2, this latest iteration of the HBM standard now supports 12-high DRAM stacks of up to 24 Gb devices, providing an aggregate stack capacity of 36 GB. With 3D stacking of memory, HBM2E provides high bandwidth and high capacity at low power and low latency in a very small footprint.
For AI/ML, HBM2E delivers an outstanding combination of features. AI training capabilities are growing at 10X per year with rapidly expanding training set sizes. With AI/ML training running in data centers that are increasingly space and power constrained, HBM2E’s compact size and low power, in combination with its unmatched bandwidth and capacity, make it an ideal solution.
To read the full article, click here
Related Semiconductor IP
- HBM2E and HBM2 FPGA IP
- HBM2E Synthesizable Transactor
- HBM2E DFI Synthesizable Transactor
- HBM2E Memory Model
- HBM2E DFI Verification IP
Related Blogs
- Complete Interface Solution for PCI Express 5.0 Launched
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions
Latest Blogs
- AI in Design Verification: Where It Works and Where It Doesn’t
- PCIe 7.0 fundamentals: Baseline ordering rules
- Ensuring reliability in Advanced IC design
- A Closer Look at proteanTecs Health and Performance Management Solutions Portfolio
- Enabling Memory Choice for Modern AI Systems: Tenstorrent and Rambus Deliver Flexible, Power-Efficient Solutions