Apple's Implications for Semiconductor
Apple's iPhone 6 alone represents at least 50K wafer starts/month plus the iPad (A8X). What could the Iphone 6S/7 & A9 mean? What about the iWatch? Apple is the technology and volume driver of the semiconductor industry so lets take a look at the broader implications.
If we do the math the A8 is 89mm2 and 8.47 X 10.5mm. Using a die calculator that means that roughly 675 die can be squeezed onto a 12 inch wafer. If we assume a 75% yield we get 500 good die per wafer (I like to use round numbers). If we take 74.5 million iPhones over three months that's about 25 million a month (or 34K an hour...but who's counting?) Divided by 500 per wafer and you get 50K wafer starts a month, give or take, depending on yield etc... That sucks up a significant chunk of a fab and doesn't leave a lot of room for other customers.
To read the full article, click here
Related Semiconductor IP
- NoC Interconnect IP Generator
- Over-Voltage Lockout (OVLO) IP
- Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
- UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
- DSP-Based 112G SerDes
Related Blogs
- How RISC-V Enables Low-Power Vision for ADAS System
- A Low-Leakage Digital Foundation for SkyWater 90nm SoCs: Introducing Certus’ Standard Cell Library
- The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
- Why SAR Radar Is Driving Renewed Demand for C-Band GaN and GaAs Front-End IP
Latest Blogs
- Building the engine behind Arm’s silicon shift
- M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C
- Understanding security certification and how analog IP can help
- Embedded Security explained: Secure boot for embedded systems
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects