Toshiba Expands SOC Design Support Network with Opening of San Diego Design Center
Continued Investment in Design Centers and Engineering Talent Demonstrates Company's Commitment to SOC Business
SAN JOSE, Calif., November 26, 2002 -- Toshiba America Electronic Components, Inc. (TAEC) today announced the opening of its seventh U.S.-based design center located in San Diego, Calif. The new design center will provide System-on-a-Chip (SOC) design implementation support and is the second design center opened by the company this year.
"Despite being in the midst of a semiconductor recession, we are committed to the SOC business and continue to invest strategically as part of our plan to grow TAEC's share of the North American market," said Richard Tobias, vice president of the ASIC and Foundry Business Unit at TAEC. "While others are faltering and cutting back, we are aggressively opening design centers and hiring top engineering talent for our development and customer support engineering organization."
The San Diego design center staff includes a highly experienced engineering team with experience in very complex, multimillion gate designs. Earlier this year, TAEC opened a new design center in Minneapolis, Minn. A large engineering team there is concentrating on mixed- signal development and design implementation for customers across the United States. This region is able to tap into a rich engineering heritage drawn from the excellent university and surrounding engineering community located there. TAEC's other design centers are located in San Jose, Calif.; Richardson, Texas; Wakefield, Mass.; Marlboro, Mass. and Beaverton, Ore.
About TAEC's SOC/ASIC Methodologies and Design Support Services
TAEC delivers high-performance, latest technology SOCs/Application Specific Integrated Circuits (ASICs) and deploys best-in-class EDA technology and methodologies that significantly improve turnaround time. TAEC offers customers a number of different design flows and methodologies to accommodate a range of customer requirements and interfaces. Carrying forward Toshiba Corporation's (Toshiba's) heritage of advanced process technology designed for manufacturability, the company is currently producing and delivering 130-namometer-generation devices in high volume.
TAEC's comprehensive engineering support before, during and after each SOC/ASIC design helps customers meet their design specifications and development schedules. Specialized engineering expertise includes customer support design engineering, EDA methodologies know-how, mixed-signal support and packaging engineering. In the case of extremely complex designs, customers can call upon expertise from Toshiba's worldwide engineering network and facilities, including Research and Development Centers.
For each design program, a TAEC engineering team is assembled to help customers create the best design based on system-chip architecture tradeoffs, silicon technology, cell libraries, IP, EDA tools, design flows, test, packaging, quality assurance and other criteria. Depending on each customer's own resources and skills, TAEC engineers can work as expert consultants or provide access to TAEC's sophisticated design tools. TAEC can also deliver turnkey engineering services to facilitate a new or derivative design.
About TAEC
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the second largest semiconductor company worldwide in terms of global sales for the year 2001 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's web site at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- Arteris Interconnect IP Selected by VeriSilicon for High-Performance SoC Design
- EnSilica joins TSMC Design Center Alliance
- Agile Analog announces MoU to support new Southern Taiwan IC Design Industry
- ASIC supplier ICsense selected for GlobalFoundries’ official design partner network
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack