Tool generates VHDL, Verilog testbenches

Tool generates VHDL, Verilog testbenches
By Richard Goering, EE Times
March 30, 2000 (2:40 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000330S0020

PLANTATION, Fla. — Visual Software Solutions has introduced HDL Bencher, a low-cost testbench generation tool that promises to turn out VHDL or Verilog testbenches without knowledge of HDL or scripting.

The tool begins by scanning VHDL or Verilog code for entity declarations. When a user selects timing parameters for synthesis tools, the tool produces a proprietary WaveTable template that combines visual waveform information with table-based data entry.

The user then describes the stimulus and expected results using a built-in pattern generator and the WaveTable spreadsheet interface. The tool exports a simulation-ready testbench, including all library declarations, stimulus and check statements, and error-reporting routines.

When the underlying HDL design is changed, the tool reimports the design and updates the waveform and testbench. The product creates dynamic testbenches that are automatically updated.

HDL Bencher for PC platfo rms costs $1,695. A limited version can be downloaded for free from the Web.