Evatronix and Avery Announce Partnership for SuperSpeed USB 3.0 IP Development and Verification

USB IP core provider and USB Verification IP developer join forces to secure first pass success for USB application designers.

Bielsko-Biala/Poland and Andover/MA, February 28th, 2011 - Evatronix SA, a leading provider of complete IP solutions, and Avery Design Systems, a renowned developer of functional verification environments today announced the signing of a partnership agreement that will be reflected in mutual help in development of USB products and continuous information exchange to better understand the requirements of USB application designers.

"Verification IP from Avery helped us pave our way in the process of USB 3.0 product development. The combination of Evatronix and Avery testing environments secured the hardware protocol verification success and, ultimately, the USB-IF certification," said Dariusz Kaczmarczyk, USB Product Line Manager at Evatronix. "With support from Avery, we can fully focus on our core business, which is IP development, and back it up with a solid verification environment provided by our partner."

"We are pleased to partner with Evatronix, who is strongly committed to deliver best in class USB device IP performance and standards compliance," said Chris Browy, VP Sales and Marketing at Avery. "Our close collaboration also better serves our mutual customers who can rely on the very best IP and VIP solutions to streamline their chip design and verification process building on a foundation of proven integration, compliance, and interoperability."

AVERY USB VERIFICATION IP

USB-Xactor is a complete verification solution consisting of SystemVerilog OVM/VMM compliant xHCI and UAS/BOT host, device, and hub models, protocol checkers, directed and random compliance test suites, and reference verification frameworks. The USB-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their designs incorporating USB host, hub, device, and PHY designs for SuperSpeed, High-Speed, Full-Speed operation. Core-level verification of USB controllers and PIPE PHY cores and full SoC-level verification is fully supported.

ABOUT AVERY

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for USB, PCI Express, SATA, and AMBA standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with leading IP vendors. Avery is a member of the PCI-SIG and USB Implementers Forum. More information about the company may be found at www.avery-design.com