Noesis Technologies Announces its Compact Area Parameterizable Reed Solomon Decoder and Encoder IP Core
November 26, 2007 -- Noesis Technologies today announced the immediate availability of its compact area parameterizable Reed Solomon Decoder and Encoder IP core (ntRS-CA). Along with its existing high throughput parameterizable Reed Solomon Decoder and Encoder (ntRS-HT), Noesis Technologies offers a complete portofolio of IP core solutions for applications that require error correction coding based on Reed Solomon algorithm.
The ntRS-HT and ntRS-CA IP cores are highly parameterizable and can be used in a variety of applications such as IEEE 802.16a, IEEE.802.16e, DVB-S, DVB-H, ITU G.984(GPON), ITU G.975, xDSL, IESS-308, CCSDS e.t.c.
The newly released ntRS-CA is especially ideal for low-power applications such DVB-H.
License options and availability
ntRS-CA is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.
About Noesis Technologies
Noesis Technologies is a leading provider of Forward Error Correction IP core solutions. Noesis Technologies specializes in the design, development and marketing of high quality, cost effective communication IP cores and provides VLSI design services. Its field of expertise include Forward Error Correction, Cryptography and Networking technology. In these fields, a broad range of high quality IP cores are offered. Noesis IP cores have been licensed worldwide and its impressive list of customers ranges from large companies to dynamic startups in diverse market sectors such as telecommunications, networking, military, industrial control and lower-power portable. For more information, visit the Noesis website at www.noesis-tech.com.
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related News
- Reed Solomon Encoder and Decoder FEC IP Core From Global IP Core
- CAST Introduces JPEG XL Encoder IP Core for High- Quality, On-Camera Still-Image Compression
- Noesis Technologies Releases DVB-H Reed Solomon Decoder
- eInfochips announces DDR2 SDRAM verification IP and Reed Solomon Encoder design IP
Latest News
- SEMIFIVE Pulls Ahead in AI ASIC Market, Expanding Lead with Successive NPU Project Wins
- M31 Reports Record NT$1.78 Billion Revenue in 2025 as Advanced Node Royalties Begin to Emerge
- Silvaco Reports Fourth Quarter and Full-Year 2025 Financial Results
- Klepsydra Technologies and BrainChip Announce Strategic Partnership to Deliver Heterogeneous AI Runtime for Akida™ Neuromorphic Processors
- Alchip Reports ASIC-Leading 2nm Developments