Rambus Announces the First 6.4 Gbps Backplane Serial Link Cell
New link architecture offers 2x the speed of existing serial link cells to break through backplane interconnect challenges
LOS ALTOS, Calif.--(BUSINESS WIRE)--June 24, 2002-- Rambus Inc., the world's leading developer of chip-to-chip interface technology, today announced the availability of the highest-speed RaSer(TM) V Serial Link cell, operating at 6.4 gigabits per second (Gbps). The RaSer V is the first cell on the market to operate at this speed and offers a proven, full-featured and easy-to-integrate solution. This solution addresses the toughest interconnect problems associated with the backplane, enabling networking, server and storage system manufacturers to double their system switching capacity while maintaining the same number of traces on the backplane.
"We expect the backplane market to increase substantially over the next three years," said Jeremy Donovan, vice president and chief analyst at Gartner Dataquest. "Factors that are driving the enterprise switch market include increasing bandwidth demands, introduction of new storage and server blades and traction of Gigabit Ethernet technology in the desktop market."
Networking customers are already integrating previous generation 1.0 - 3.2 Gbps RaSer cells into their product designs, taking advantage of the extremely low power and area consumption. Rambus developed a completely new serial link architecture using standard bi-level signaling to meet customer demand for 6.4 Gbps cells that can be integrated on low cost, CMOS processes.
The new RaSer V 6.4 Gbps cell delivers a complete feature set, ideally suited for the harsh backplane environment and includes:
- Wide serial data rate range: 2.5 Gbps to 6.4 Gbps
- Backward compatible to 3.2 Gbps:
- Easy integration in ASICs and ASSPs
- Multi-tap transmit and receive equalization
- Calibrated termination resistors
"System designers want maximum speed per pin to increase system capacity within the constraints of space, power and cost," said Kevin Donnelly, vice president of the Network Connections Division at Rambus Inc. "With the introduction of this 6.4 Gbps Serial link cell, Rambus is driving the transition of the next generation backplane"
The RaSer V 6.4 Gbps cell is currently being demonstrated by Rambus and is available in standard TSMC .13u process for licensing and integration into customer designs.
RaSer(TM) Cell Technology
Rambus RaSer technology is a physical layer underlying a broad range of industry standards and offers designers a scalable serial link architecture that addresses current and future serial link applications requiring the highest bandwidth. RaSer technology can be employed across a variety of different networking applications, including WAN router and switch backplanes, Gigabit and 10-Gigabit Ethernet, InfiniBand, Fibre Channel, and fiber optic network interfaces and any other custom chip-to-chip applications.
Rambus RaSer cells are offered as an analog core library cell, for ASIC and ASSP designs. A complete serial link solution, the RaSer cell contains serializer, transmitter, receiver, deserializer, and clock recovery circuitry. The cell is designed to meet the physical layer requirements for a wide range of serial link applications, each of which may have different logical requirements (protocol, framing, coding, etc.). As a replacement to stand-alone discrete serial link components, the RaSer cell may be integrated with other communications functions in order to offer higher value network services and reduced component count.
For more information on RaSer technology, visit Rambus' web site at www.RaSerLink.com.
About Rambus Inc.
Rambus is the leading developer and marketer of breakthrough chip-to-chip interface technology, products and solutions to the electronics industry. The company licenses its technology in the form of ASIC cells that are incorporated into high-performance memory and logic chips by 25 of the world's top semiconductor makers. The company's ASIC cells and system-level solutions are incorporated into electronic products, including personal computers, workstations, video game consoles, network routers, HDTVs and set-top boxes.
Rambus and RaSer are registered trademarks of Rambus Inc. Other trademarks that may be mentioned in this release are the intellectual property of their respective owners.
This press release contains forward-looking statements. These statements are based on current expectations, estimates and projections about the Company's industry, management's beliefs, and certain assumptions made by the Company's management.
You can identify these and other forward-looking statements by the use of works such as "may", "will", "should," "expects," "plans," "anticipates," "believes," "estimates," "predicts," "intends," "potential," "continue" or the negative of such terms, or other comparable terminology. Forward-looking statements also include the assumptions underlying or relating to the foregoing statements. Actual results could differ materially from those anticipated in these forward-looking statements as a result of various factors, including those identified in the Company's recent filings with the Securities and Exchange Commission, including its recently filed Form 10-Q, and also including the uncertainty of new technologies; and the uncertainty regarding the technical and market demands for such technologies. All forward-looking statements included in this press release are based on information available to Rambus on the date hereof. Rambus assumes no obligation to update any forward-looking statements.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related News
- Rambus Announces Industry's First 10 Gbps Backplane Serial Link Solution
- Trebia Networks Debugs 4 Gbps Integrated Storage Network Processor Chip SNP-1000 with LogicVision's Validator
- Rambus and Teradyne to Demonstrate 10 Gbps Backplane Solution at DesignCon East 2003
- Toshiba Unveils Serial Link Cell Agreement with Rambus Targeting Backplane and Fibre Channel Applications
Latest News
- HPC customer engages Sondrel for high end chip design
- PCI-SIG’s Al Yanes on PCIe 7.0, HPC, and the Future of Interconnects
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- Cadence Unveils Arm-Based System Chiplet
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers