Creonic Celebrates 1,000 Downloads of its Open Source Viterbi Decoder IP Core
1,000 Viterbi Decoder IP Core Downloads in Six Months
July 16 2012 -- Today Creonic celebrates 1,000 downloads of its open source Viterbi decoder IP core from the OpenCores platform. "We are thrilled about the huge interest in our open source IP core", says Matthias Alles, CEO of Creonic. He adds, "It took less than six months to achieve this milestone".
The VHDL source code of the Creonic Viterbi decoder is published under the GPL license. It is adaptable to many standards of communications, e.g., GSM, UMTS, CDMA, WiMAX, and WiFi. The AXI4-Stream interface allows simple integration. Shortly after publication OpenCores awarded the IP core the OCCP certificate emphasizing that the core is stable and satisfies an abundance of quality criteria.
The publication under GPL makes it possible to use the IP core free of charge and enables the adaptation of the decoder to individual needs. Besides support, Creonic offers commercial licenses that grant the user of the IP core more rights than the GPL.
About Creonic
Creonic provides IP cores as ready-for-use solutions for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The product portfolio covers standards like DVB-S2, DVB-C2, WiFi, UWB, and GMR. Our products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance.
Viterbi decoder at Creonic
Related Semiconductor IP
Related News
- SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
- Bluespec Unveils Groundbreaking "RISC-V Factory" - Empowering Open Source Hardware Developers to Build Faster and More Efficiently
- Bluespec, Inc. to Open Source Its Proven BSV High-level HDL Tools
- The BSC coordinates the manufacture of the first open source chip developed in Spain
Latest News
- IObundle Promotes IOb-Cache: Premier Open-Source Cache System for AI/ML Memory Bottlenecks
- Quintauris Secures Capital Increase to Accelerate RISC-V Adoption
- MIPI Alliance Releases UniPro v3.0 and M-PHY v6.0, Accelerating JEDEC UFS Performance for Edge AI in Mobile, PC and Automotive
- Marvell to Showcase PCIe 8.0 SerDes Demonstration at DesignCon 2026
- Embedded FPGA reaches a new stage of industrial maturity – Menta at Embedded World 2026