Oasys Announces New Funding Led by Intel Capital, Xilinx and former Cadence CEO Joe Costello
July 25, 1013 - Oasys Design Systems announced they have raised a new round of funding led by Intel Capital, Xilinx and former Cadence CEO, Joe Costello. Funds will be used to expand the company’s sales, marketing and product development activities
Related Semiconductor IP
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
Related News
- Exclusive CEO Interview: Latest Funding Drives Ventana's First RISC-V Chiplets in Data Centers
- Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process
- Intel CEO Voices Concerns About CHIPS Funds, Export Controls
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
Latest News
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool
- SkyWater Technology and Silicon Quantum Computing Team to Advance Hybrid Quantum-Classical Computing
- Dnotitia Revolutionizes AI Storage at SC25: New VDPU Accelerator Delivers Up to 9x Performance Boost