Mentor package helps verify TI DSPs
By
February 24, 2004 (11:14 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010227S003961
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- TI fires up C64X-based DSPs for 3G wireless run
- Intel's XScale platform takes shot at TI DSPs
- 0-In Design Automation Helps AMD Verify Complex Networking and Processor Chipsets
- Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity
Latest News
- Silicon Creations Celebrates 20 Years of Global Growth and Leadership in 2nm IP Solutions
- TSMC Debuts A13 Technology at 2026 North America Technology Symposium
- Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon
- Synopsys Partners with TSMC to Power Next-Generation AI Systems with Silicon Proven IP and Certified EDA Flows
- JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory