Mentor package helps verify TI DSPs
![]() |
By
February 24, 2004 (11:14 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010227S003961
Related Semiconductor IP
- Xtal Oscillator on TSMC CLN7FF
- Wide Range Programmable Integer PLL on UMC L65LL
- Wide Range Programmable Integer PLL on UMC L130EHS
- Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
- Wide Range Programmable Integer PLL on TSMC CLN80GC
Related News
- TI fires up C64X-based DSPs for 3G wireless run
- Intel's XScale platform takes shot at TI DSPs
- 0-In Design Automation Helps AMD Verify Complex Networking and Processor Chipsets
- Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity
Latest News
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- The world’s first open source security chip hits production with Google
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing