Mentor package helps verify TI DSPs
By
February 24, 2004 (11:14 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010227S003961
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related News
- TI fires up C64X-based DSPs for 3G wireless run
- Intel's XScale platform takes shot at TI DSPs
- 0-In Design Automation Helps AMD Verify Complex Networking and Processor Chipsets
- Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity
Latest News
- QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC
- Creonic Updates Doppler Channel IP Core with Extended Frequency Band and Sampling Range
- TSMC Price Hikes End the Era of Cheap Transistors
- Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets
- Codasip RISC-V processors certified up to ASIL-D