0-In Design Automation Helps AMD Verify Complex Networking and Processor Chipsets

0-In products find clock domain crossing and shared resource bugs

SAN JOSE, Calif. -December 17, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced that its products were used to help successfully verify two complex chipsets at the Dresden Design Center of AMD (NYSE: AMD). These design projects used all the tools in 0-In's Assertion-Based Verification (ABV) Suite to enable faster and more thorough functional verification.

"The chips we develop are highly complex, containing control and data structures with many corner-case behaviors that occur only in very specific circumstances," said Frank Dresig, manager of the Design/Verification Department at the Dresden Design Center of AMD Saxony. "We selected the 0-In tools to improve our overall development process by adding assertions and formal verification. We were pleased with the results: we increased our tape-out confidence and helped improve our time-to-market, which translated directly to project cost savings."

The first project using the 0-In ABV Suite was an I/O hub, part of a chipset for the AMD Athlon™ 64 and AMD Opteron™ processors. Currently marketed by AMD as the AMD-8111™ HyperTransport™ technology I/O Hub, the chip connects to the host via the high-speed HyperTransport technology bus and provides connectivity to a wide range of other interfaces, including PCI, USB, LPC, IDE and 10/100 Ethernet. The second project was a network controller that bridges from a PCI interface to wireless Ethernet using the IEEE 802.11b standard. This chip is currently available from AMD as Am1771™, part of the AMD Alchemy™ Am1772™ Wireless LAN Chipset.

0-In Checklist Verifies Clock Domain Crossings
One of the biggest challenges for complex chip designs is verifying that signals crossing between different clock domains are properly synchronized. 0-In Checklist includes sophisticated analysis for clock domain crossing (CDC) as part of its automatic checks for common types of design errors. Because of its many standard interfaces, each of which runs on an independent clock, the AMD team chose the AMD-8111 chipset as the focus for CDC verification. "0-In Checklist was very easy to integrate into our overall verification methodology," said Mr. Dresig. "One interesting 0-In detection was a case of re-convergence, in which two independently synchronized signals were combined into the same logic. We were able to track down the problem easily, fix the synchronization, and re-run CDC analysis to verify that the error was fixed correctly."

Checkers in Simulation Improve Verification Efficiency
In the 0-In methodology, assertions are specified within the RTL design files using elements from the CheckerWare library. "We added about 50 checkers in the AMD-8111 chipset component design and about 200 checkers in the AMD Alchemy Am1772 wireless LAN chipset project," reported Mr. Dresig. "It was easy to understand the CheckerWare library and easy to choose appropriate checkers to capture our ideas for assertions." 0-In also provides CheckerWare monitors for many standard interfaces; the AMD-8111 project used the HyperTransport technology, PCI and LPC monitors to help verify conformance to these protocols. The AMD team used 0-In Check to convert the CheckerWare assertions and monitors into simulation checkers that ran in all their block-level and chip-level simulations. This enabled the engineers to increase the observability of their designs, determine structural coverage metrics and detect bugs at the source.

0-In Formal Verification Tools Find Corner-Case Bug
The 0-In Confirm static formal verification tool and the 0-In Search dynamic formal verification tool can find corner-case bugs missed in simulation and increase tape-out confidence when no more bugs are found. "We targeted the MAC block in the Am1772 project for formal verification since we knew that it would be hard to verify adequately with simulation alone," said Mr. Dresig. "When we ran 0-In Search on this block, it detected a tough-to-find corner-case bug in which access to a set of shared resources was not granted in the right order. We consider 0-In Search a valuable component of our overall verification strategy." After this bug was fixed, the team ran both 0-In Search and the deeper formal analysis of 0-In Confirm to verify that the fix was correct and that there were no additional bugs in the design.

Case Study Available in Chip Design Magazine
Complete details of these two projects are available in an article entitled "Assertions Enter the Verification Arena" written by the AMD Dresden design team for the December issue of Chip Design magazine. The article is also available on the magazine's web site at http://www.chipdesignmag.com and on 0-In's web site at http://www.0-in.com/news.html.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution built on industry standards that provides value throughout the design and verification cycle - from the block level to the chip and system levels. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

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