LEON3 has passed SPARC V8 compliance testing
-- LEON3 has passed SPARC Architecture Version 8 compliance testing on May 1, 2005 and has been declared SPARC V8 Compliant.
The LEON3 is the more performant successor of the LEON2 processor capable of delivering 400 MIPS on a 0.13 um process. The successful compliance testing is yet another milestone in our continuous development of SPARC processors, says Jiri Gaisler, CTO and founder of Gaisler Research.
The SPARC (Scalable Processor Architecture) is the industry's only openly defined and evolved RISC architecture. Unlike other RISC (Reduced Instruction Set Computer) designs, SPARC specifies not a hardware implementation ("chip"), but an open, standard architecture belonging to the community of SPARC vendors and users. The SPARC specification is defined by the SPARC Architecture Committee, a technical arm of the computer-maker consortium, SPARC International.
About Gaisler Research AB
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. The Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP-cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- Atmel Introduces the AT697F Radiation-Hardened SPARC V8 Processor for Space Missions
- Innopower Technology Corp. Announces the Availability of USB 3.0 Physical Layer (PHY) IP Which Has Passed USB-IF SuperSpeed Certification, through Customers' Solutions
- Cadence Announces TripleCheck IP Validator for Faster IP Compliance Testing
- Northwest Logic's PCI Express 3.0 Solution passes PCI-SIG PCIe 3.0 Compliance Testing at First Official PCIe 3.0 Compliance Workshop
Latest News
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP
- Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects