Innoveda latches onto XML for design

"It's not only higher level than approaches such as SystemC, it's broader too and offers a way of capturing constraints as well as design data that is not locked d own to one particular space, whether it is hardware or software," Herman said. The company will open up the specification for the XML schema-structures and tags that make up valid design elements — if it gains enough support from customers.

"You can't be successful owning a would-be standard. Our goal is to find a methodology, not to create the actual unifying language. XML certainly has the capability to act as a unifying language," said Herman.

Herman does not see XML as the only language used in system modeling at a high level. He said there would be little point in converting existing Verilog or VHDL design files into their XML equivalents purely for co-simulation. Instead, tools will produce the XML descriptions to capture specs for modules yet to be implemented.

"XML suffers in that it is very big and very slow. We can take a small subset of a chip in Verilog and describe it in XML, but it is 100 times larger. The chances are that we will see multiple languages," said Herman.

At th is June's Design Automation Conference, Innoveda plans to roll out its first tools based on technology developed by Viewlogic and combined with Summit's existing Visual products. The tools will support system simulation using a mixture of C, C++ and SystemC.

— Chris Edwards is a contributing editor with Electronics Times, EE Times' sister publication in the U.K.