Mentor CEO: IC design costs to hit $100M
Mark LaPedus, EE Times
(03/03/2010 1:12 PM EST)
SAN JOSE, Calif. -- Chip design costs are expected to soar, but software--not hardware--is playing a much greater role in the problematic equation, according to the top executive of Mentor Graphics Corp.
The shift in the equation will require a new type of EDA technology-- embedded software automation (ESA)--as a means to attack the problem, said Walden Rhines, chairman and chief executive of Mentor.
Rhines warned that IC design costs for many devices are projected to hit the dreaded $100 million level within the next three years. Not long ago (and even today), IC design costs ranged between $20-to-$50 million
To read the full article, click here
Related Semiconductor IP
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
Related News
- Robust AI Demand Drives 6% QoQ Growth in Revenue for Top 10 Global IC Design Companies in 1Q25
- Secure Your IC Design Project Slot with CoreHW for Q4 2025 & 2026
- SynTest rolls out design-for-test software to reduce chip-testing costs
- DFT software tackles test costs <!-- verification -->
Latest News
- Announcing Arm Performix: Empowering developers with scalable performance for the age of AI agents
- MIPI Alliance Launches Physical AI Birds of a Feather (BoF) Group Focused on Humanoids
- Faraday Reports First Quarter 2026 Results
- Cadence Reports First Quarter 2026 Financial Results
- Rambus Reports First Quarter 2026 Financial Results