eSilicon announces 7nm FinFET ASIC design win
High-speed networking ASIC based on complete TSMC 7nm IP platform
SAN JOSE, Calif. — January 9, 2018 — eSilicon, an independent provider of FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, today announced its first 7nm design win at a major OEM. The design win follows eSilicon’s development of a complete IP platform on TSMC 7nm process technology for high-bandwidth networking, high-performance computing and AI applications. The 7nm IP platform includes a 56G long-reach SerDes, TCAM, HBM2 PHY, high-speed fast cache, single-port and dual-port SRAMs and many high-speed, high-density multi-port memory architectures.
The design win was enabled by the power and performance profile of TSMC’s 7nm process technology. As compared to TSMC’s 16FF+ technology, 7nm provides a 35% speed gain at the same power or 60% power reduction at the same speed. These factors helped to address the demanding requirements of this advanced data center chip.
“Advanced data center chips consistently push the envelope for higher performance at lower power,” said Jack Harding, president and CEO of eSilicon Corporation. “TSMC’s 7nm technology provided the right balance of power reduction and performance improvement to address these demands.”
About eSilicon
eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- eSilicon Tapes Out 7nm 400G Gearbox/Retimer Test ASIC
- TSMC Certifies Synopsys Design Platform for High-performance 7-nm FinFET Plus Technology
- Mentor enhances tool portfolio for TSMC 5nm FinFET and 7nm FinFET Plus processes and Wafer-on-Wafer stacking technology
- 7nm networking platform delivers unprecedented performance and configurability for data center ASICs
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack