DesignCon: Nvidia's engineering VP wants better design tools
Brian Fuller, EETimes
1/29/2013 6:10 PM EST
SANTA CLARA, Calif.--Cultural complacency and "uncomplaining" engineers are stunting EDA tool investment and preventing IC companies from keeping up with quickening design complexity, a senior engineering manager at chip vendor Nvidia Corp. said Tuesday (Jan. 29).
"Engineers don't complain enough," said Jonah Alben, Nivida's senior vice president of engineering, said during a keynote address at the DesignCon conference here.
To read the full article, click here
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- Green Plug Appoints Kevin Jones to New Post of Chief Scientist, Names Rajeev Prasad VP of Engineering
- Flex Logix Appoints Abhijit Abhyankar as VP Silicon Engineering
- Sidense Hires Industry Veteran Ken Wagner as Senior VP Engineering
- HHGrace and Empyrean Continue Their Cooperation on Local EDA Tools to Facilitate IP Design
Latest News
- Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP