NetEffect Adopts Denali's PCI Express 2.0 and IO Virtualization Technology Solutions
PALO ALTO, Calif. -- Nov. 6, 2007
-- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that NetEffect, the leader in high performance, low power Ethernet connectivity solutions, has standardized on Denali Databahn(TM) PCI Express (PCIe) design cores and PureSpec(TM) verification IP, which support the latest PCIe 2.0 and I/O virtualization (IOV) specifications from the PCI-SIG, for use in developing their next-generation accelerated multi-gigabit Ethernet adapters. NetEffect architects and engineers use Denali's Databahn IP cores and PureSpec verification IP products to accelerate the design and verification of these systems, and speed overall deployment of PCI Express IOV technology.
"NetEffect was pleased with Denali's PureSpec PCIe VIP solutions for PCIe 1.1 and has expanded our relationship by embracing Denali's PCIe 2.0 design IP and verification IP solutions," said Terry Hulett, vice president of Engineering at NetEffect. "Denali's PCIe core and PureSpec verification IP are integral enablers in meeting the PCIe Gen 2.0 specifications. Today's demanding data center networks address their increasing traffic needs by incorporating our latest accelerated 1Gb and 10Gb Ethernet products. Denali's reputation and track record speaks volumes for creating and delivering high-quality, complete IP solutions for the latest process technologies."
IOV is a key technology that enables systems to simultaneously share PCI Express (PCIe) resources within multi-CPU systems, or across multiple operating systems. Large data centers and large storage environments use IOV technology to increase performance and reduce overall power and system costs.
"Our industry-leading PCI Express IO virtualization technology and verification IP will enable NetEffect to achieve their high throughput and feature requirements," states David Lin, vice president of product marketing for Denali. "Our customers, like NetEffect, can depend on our high-quality, interoperable design and verification IP solutions and excellent customer support to meet their product development timeframes and achieve a competitive advantage."
Denali's Databahn PCIe cores and PureSpec verification IP software for PCI Express provide full support of the Address Translation Service specification, Single-Root I/OV, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities. For more info about Databahn and PureSpec, visit http://www.denali.com/products.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Related Semiconductor IP
- PCIe - PCI Express Controller
- Scalable Switch Intel® FPGA IP for PCI Express
- Multichannel DMA Intel FPGA IP for PCI Express*
- PCI Express Gen5 SERDES PHY on Samsung 8LPP
- PCI Express Gen4 SERDES PHY on Samsung 7LPP
Related News
- TES Unveils High-Performance 8/40MHz Oscillator and Clock Buffer IPs for Reliable On-Chip Timing Solutions for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Denali Announces Availability of PCI Express I/O Virtualization Solutions
- Denali Announces Complete Bundle of I/O Virtualization Technology Solution With PureSpec PCI Express Verification IP
Latest News
- Arasan Announces immediate availability of its UFS 5.0 Host controller IP
- Bolt Graphics Completes Tape-Out of Test Chip for Its High-Performance Zeus GPU, A Major Milestone in Reducing Computing Costs By 17x
- NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory
- M31 Collaborates with TSMC to Achieve Tapeout of eUSB2V2 on N2P Process, Advancing Design IP Ecosystem
- Menta’s eFPGA Technology Adopted by AIST for Cryptography and Hardware Security Programs