Cadence Offers Production Proven USB 3.0 Host Controller IP
USB Design IP is Used in Industry Standard Compliance Program
SAN JOSE, Calif, 27 May 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that a production proven host controller intellectual property (IP) for USB 3.0 has been added to the Cadence IP offering. The Cadence® USB 3.0 xHCI host controller IP was originally developed by Fresco Logic, a global fabless semiconductor company that develops and markets advanced connectivity solutions. This design IP is used as part of a recommended Peripheral Development Kit (PDK) for compliance testing by the USB Implementers Forum (USB-IF) and has been deployed in over a billion USB ports. Being part of the compliance test ensures interoperability with the large number of USB peripheral controllers available in the market.
Now licensed by Cadence, the USB 3.0 xHCI host controller is being offered as fully supported semiconductor IP as part of Cadence's complete USB IP and VIP solution. Cadence also has an agreement with Fresco Logic to license the next generation of this host controller IP supporting the USB 3.1 protocol.
"This USB 3.0 host controller IP is tried and true, has been a part of SuperSpeed compliance testing from the start and utilized as a discrete IC in many production systems," said Robert McVay, CTO of Fresco Logic. "With Cadence licensing and supporting it as part of their full USB portfolio, their customers have the immediate benefit of a proven high-performance, low-risk, and lower cost solution for USB 3.0 host applications."
"The addition of the USB 3.0 and USB 3.1 xHCI host controller IP completes the Cadence USB portfolio, complementing our premium USB PHY design in the most advanced process nodes," said Martin Lund, senior vice president, IP Group, of Cadence. "Our customers now have immediate access to a complete solution that enables their products to work effectively, meet compliance quickly, and get their products to store shelves sooner, further reinforcing our continued investment in leading-edge interface IP solutions."
The Cadence USB 3.0 IP is fully configurable, allowing customers to achieve the optimized functionality they require, whether it is for mobile or infrastructure applications. For more on the USB IP family, please visit: http://ip.cadence.com/ipportfolio/interface-ip/usb-ip. Complementing this solution, Cadence also offers USB Verification IP. To learn more, please visit: www.cadence.com/news/usb3simulationvip.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
Related Semiconductor IP
- SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
- Super Speed USB 3.0 Extensible Host Controller xHCI
- USB 3.0 xHCI Host Controller
- USB 3.0 High/Full/Low-Speed Host + Device Controller IP
- USB 3.0 Gen1 / Gen2 Host Controller IP
Related News
- Cadence USB 3.0 Host Solution on TSMC 16nm FinFET Plus Process Achieves Industry Certification
- USB 4.0, USB 3.2, USB 3.1, USB 3.0, USB 2.0, Device, Hub, Host & Dual Mode proven Interface IP Controllers are available immediately to License
- USB 4.0 Host and Device Controller IP Cores unleashing the Power of High-Speed Connectivity with tunnelling of Display Port and PCIe is now available for Licensing
- DI3CM-HCI, A High-Performance MIPI I3C Host Controller IP Core for Next-Generation Embedded Designs
Latest News
- ASICLAND Partners with Daegu Metropolitan City to Advance Demonstration and Commercialization of Korean AI Semiconductors
- SEALSQ and Lattice Collaborate to Deliver Unified TPM-FPGA Architecture for Post-Quantum Security
- SEMIFIVE Partners with Niobium to Develop FHE Accelerator, Driving U.S. Market Expansion
- TASKING Delivers Advanced Worst-Case Timing Coupling Analysis and Mitigation for Multicore Designs
- Efficient Computer Raises $60 Million to Advance Energy-Efficient General-Purpose Processors for AI