Dolphin Integration measures 15% area reduction on 65 nm logic circuit with its 6-Track standard cell library
Grenoble, France – September, 21 2012 -- Dolphin Integration today announced the availability of benchmark results on real conditions at TSMC 65 nm LP process, comparing its SESAME uHD-BTF DV standard cell with a 7-Track library:
Highlights:
- SESAME uHD-BTF DV standard cell is 9% to 15% denser after P&R compared to standard 7-Track Library
- Leakage power is reduced 6 times in worst case conditions (SS; 1.08 V; -40°C)
- Low Voltage Capability for additional power savings when operating down to 0.9 V +/-10%
SESAME uHD-BTF DV benefits from replacing classical D flip-flops with pulsed latches acting as “spinner cells”. The main advantage of the spinner cell is a significant improvement in terms of density, 30% compared with D flip-flops!
More information on the key benefits of SESAME uHD-BTF DV standard cell library is available directly on the Presentation sheet
To request an access to the evaluation kit of SESAME uHD-BTF DV standard cell, contact sesame@dolphin-integration.com
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, such as mixed signal high-resolution converters for audio and measurement applications, Libraries of memories and standard cells, Power management networks, Microcontrollers. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related News
- Dolphin Integration announce availability of their 6-Track Standard Cell Library SESAME HD for the 65 nm LP process
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- NASA Selects Ridgetop Group to Develop an Innovative Modular SiGe 130 nm Cell Library
- Dolphin Integration announce the availability of new ROM TITAN and ultra low leakage standard cell library SESAME BIV at TSMC 55 nm LP eFlash
Latest News
- Virtusa Acquires Bengaluru based SmartSoC Solutions, Establishing Full-Stack Service Offering from Chip to Cloud and Driving Expansion into the Semiconductor Industry
- Consumer Electronics and AI Product Launches Lift 3Q25 Top-10 Foundry Revenue by 8.1%, Says TrendForce
- Joachim Kunkel Joins Quadric Board of Directors
- RaiderChip NPU leads edge LLM benchmarks against GPUs and CPUs in academic research paper
- SEMIFIVE Secures AI Semiconductor Design Projects in Japan, Accelerating Global Expansion with New Local Subsidiary